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[01.26.2010]
NEC Ups Frequency With PTL Interconnects.
NEC Electronics (Tokyo) engineers faced a conundrum in development of the RF circuits created on a 40 nm CMOS technology. The copper contact plugs used in the logic portions of system-on-a-chip (SoCs) wireless products to reduce capacitance were not ideal for the analog and RF portions of long-term evolution (LTE) and WiMax solutions.
Yoshihiro Hayashi, an NEC research fellow, said 4G wireless SoC solutions require high-performance analog and RF transistors, capable of an Fmax of ~200 GHz. Currently, 4G solutions require multichip modules, but efforts are underway to shrink to single-chip solutions.
In 2008, NEC developed a copper double-damascene (Cu-DD) contact structure that
read more
[01.21.2010]
MIRAI Advances Ge Transistor Prototype
The Millennium Research for Advanced Information Technology (MIRAI, Tsukuba, Japan) consortium has unveiled a germanium p-type transistor aimed at the 2X generation of process technology and beyond. The Japanese research consortium said the germanium transistor includes a LaAlO3 high-k dielectric, a Schottky barrier source junction, and a shallow junction with a boron stop layer.
The prototype is produced on a bulk germanium material, but later the transistor will be fabricated with a Ge-on-Si substrate. In the early days of the semiconductor industry, germanium was replaced by silicon partly because germanium lacked a stable native oxide, a challenge now being resolved
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[01.11.2010]
Emerging Trends in Advanced Packaging
Among the many packaging challenges that must be addressed is the continued development of powerful co-design tools to shorten development cycles, and enhance
performance and reliability. Continued pitch reductions and the use of 3-D package interconnects in single-chip and multichip components, and IC integration with sensors, energy harvesting and biomedical devices require packaging materials that are low cost and can be easily processed.
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